Value proposition
We demonstrated that by selecting the optimal gate current profiles, it is possible to reduce the switching losses by up to 63 %, while maintaining the same overshoot or slew rate as with a classical gate driver. These optimized profiles can be stored in a lookup table and later used to generate the appropriate gate current waveforms depending on the operating conditions.
Business and innovation perspective
We are addressing the challenge of optimally controlling silicon carbide (SiC) metaloxide-semiconductor field-effect transistors (MOSFETs) to minimize switching losses and simultaneously reducing overshoots and voltage slew rates.
For our research, we used a double pulse test circuit for running simulations in SIMetrix. The circuit contains a MOSFET model which, in the classical case, is driven by a pulse voltage source. A high level voltage turns the MOSFET on, and a low level voltage turns it off. These transitions are not instantaneous, and requires a certain amount of energy, which we want to minimize. In addition, we must ensure that overshoots and slew rates remain within safe limits to avoid damaging the MOSFET or creating excessive electromagnetic interference. In the classical driving approach, these factors are regulated by adjusting the gate resistance: smaller values reduce switching losses but increase overshoots, while larger values do the opposite. A compromise is required to meet the circuit performance criteria, which remain limited because of the restricted controllability of the switching waveforms.
To achieve both lower losses and lower overshoots, we replace the traditional voltage source with a programmable gate current source, which generates a sequence of pulses for the turn-on and turn-off phases. Each pulse is defined by its amplitude and width, and by adjusting these parameters, we can obtain different switching behaviors and optimize the performance of the MOSFETs.
To identify the optimal gate current profiles without running an excessive number of simulations, we developed a sequential lowest segment extraction (SLSE) algorithm. The main idea is to start from an initial gate current profile and then systematically adjust two of its parameters to follow the Pareto curve. In the turn-on phase, these parameters are the durations of the pulses, while in the turn-off phase, they are the duration of the first pulse and the amplitude of the second pulse.
Technical specification
No hardware devices or physical equipment were developed as part of the project.